1. Field of the Invention
The present invention relates to computer system architectures. More particularly, the present invention relates to interrupt signaling by components within a computer system.
2. Art Background
In the computer industry, one widely accepted system architecture for personal computers has been the AT system design. Prior systems incorporating this architecture included system buses implementing the ISA, and then later, the EISA bus protocols. This protocol defines fifteen distinct system interrupts for use by various components within the system. These interrupts, by convention, are denoted IRQ0 through IRQ15 with one of the IRQ signals, such as IRQ2 being dedicated for internal use by the system's programmable interrupt controller. In a conventional implementation, these are edge-triggered interrupt signals provided by a system component or peripheral to the computer system's interrupt controller.
The above described computer systems that implement the ISA or EISA bus protocol interrupt mechanisms generally incorporate an interrupt controller that receives the various IRQ signals and, in response thereto, provides a signal to the system's central processing unit (CPU) indicating the existence of a pending interrupt. The CPU, in response to an active interrupt signal, acknowledges the interrupt signal to the interrupt controller whereupon the interrupt controller provides a code vector to the CPU for executing the appropriate interrupt service routine (ISR). One well known programmable interrupt controller mechanism is one which implements two Intel 8259 peripheral interrupt controllers.
In the one embodiment, each of the two 8259 peripheral interrupt controllers is capable of receiving eight distinct IRQ signals. To support the full range of IRQ signals [0:15], the first 8259 controller is configured to receive IRQs 8-15 and generate an interrupt signal output as response thereto. The output of the first 8259 controller is then provided as one of the IRQ inputs such as IRQ0 to a second 8259 controller with the other seven inputs coming from other system components. The second 8259 controller in the programmable interrupt controller mechanism (PIC) supplies its output to the CPU. In this manner, two 8 IRQ input peripheral interrupt controllers are chained together to provide for 15 possible IRQ signals within the system.
The above interrupt signaling protocol suffers some unfortunate disadvantages. Particularly, it anticipates a rigid assignment of IRQ signals that are also of a predetermined type (i.e., edge-triggered interrupts). In addition, it is not conducive to the sharing of interrupts and thus limits the total number of peripherals that might indicate a pending interrupt request to a system's CPU. These concerns are magnified in developing systems where portability and low pin count constraints are considerations that are paramount. It would be desirable, and is therefore an object of the present invention, to provide flexibility in interrupt signaling which reduces peripheral pin count necessities as well as provides for the sharing of system interrupts and configurability without increasing the complexity of a peripheral's interconnections to the interrupt mechanism of a computer system.